The present invention relates in general to semiconductor fabrication methods and resulting structures. More specifically, the present invention relates to methods of fabricating vertical transport field effect transistors including a sacrificial doped layer for forming the top source/drain extension regions.
Field effect transistors (FETs) are commonly employed in electronic circuit applications. FETs can include a source region and a drain region spaced apart by a semiconductor channel region. A gate, potentially including a gate dielectric layer, a work function metal layer, and a metal electrode, can be formed above the channel region. By applying voltage to the gate, the conductivity of the channel region can increase and allow current to flow from the source region through the channel to the drain region.
Vertical Transport FETs (VTFET) are one of the promising alternatives to standard lateral FET structures due to benefits, among others, in terms of reduced circuit footprint. VTFETs employ semiconductor fins and side-gates that can be contacted outside the active region, resulting in increased device density and some increased performance over lateral devices. In VTFETs, the source to drain current flows in a direction that is perpendicular to a major surface of the substrate. For example, in a known VFET configuration a major substrate surface is horizontal and a vertical fin extends upward from the substrate surface. The fin forms the channel region of the transistor. A source region and a drain region are situated in electrical contact with the top and bottom ends of the channel region, while a gate is disposed on one or more of the fin sidewalls.